1. Field
Example embodiments relate to a non-volatile semiconductor memory device More particularly, embodiments relate to a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation.
2. Description of the Related Art
If a speed of a write operation is slower than a speed of a read operation in a non-volatile semiconductor memory device, an ability of the non-volatile semiconductor memory device is reduced or limited due to a difference between the speed of the write operation and the speed of the read operation. As a result, a non-volatile semiconductor memory device performing a read-while-write operation may be used. The non-volatile semiconductor memory device may perform the read operation while performing the write operation in order to overcome, reduce or limit the difference between the speed of the write operation and the speed of the read operation.
Generally, the non-volatile semiconductor memory device performing the read-while-write operation may include a memory cell array having a plurality of memory cells. The semiconductor memory device may also include a plurality of local bit-lines coupled to the memory cells, a plurality of global write bit-lines for writing data into the memory cells, and a plurality of global read bit-lines for reading data from the memory cells. A global write bit-line and global read bit-line may be paired and/or coupled to a local bit-line through a local column selection unit.
Since a pair of the global write bit-line and the global read bit-line is coupled to the local bit-line during the read-while-write operation of the non-volatile semiconductor memory device, a coupling phenomenon between a discharge operation of the global write bit-line coupled to the local bit-line for the write operation may occur. Also, a develop operation of the global read bit-line coupled to the local bit-line for the read operation may occur if the non-volatile semiconductor memory device performs the read-while-write operation. As a result, the non-volatile semiconductor memory device may provide lower operation reliability and lower operation stability.